ES660 ESD Electrostatic Discharge and Latch Testing System

ESDMEC Technology LLC was founded by Wei Huang in March 2011 in Rolla, Missouri, USA.ESDMEC develops ESD and EMC solutions. The company is committed to providing innovative, advanced, high-quality, and cost-effective solutions, as well as general consulting, testing services, and customized projects.The product includes charging equipment model (CDM) system, cableDischarge Event (CDE) system, ESD simulator, pulse attenuator, current probe, TEM battery for RF transmission/immunity, high-voltage DC power supply, customized high-voltage/RF design.ESDMEC Technology has been a corporate member of the ESD Association since 2012.

ES660 ESD Electrostatic Discharge and Latch Testing SystemIt is an advanced multi needle automatic testing equipment. Designed to meet the stringent requirements of modern semiconductor testing. productThe testing capability ensures efficient evaluation of large-scale devices, significantly reducing testing time and improving production efficiency.

Specially designed to meet the stringent requirements of modern semiconductor testing. This multifunctional device can fully support human discharge model (HBM), machine model (MM), latch (LU), and transient latch (TLU) testing, providing a complete solution for reliability evaluation of integrated circuits (IC) and electronic components. Compared to the old solution of ES612A+RE64 relay expansion module/ES660-P1-EM1 ATE expansion module, ES660 has a higher specification configuration. The ES660-P1 basic configuration supports 128 to 1024/1280 pins and 10 buses, making it an ideal hardware platform for testing multi interface integrated circuits and electronic components. For higher pin count testing requirements, ES660-P1 can be upgraded to ES660-P2 configuration. This configuration uses a high-density host motherboard that supports up to 2560 pins and 12 buses. The rated voltage of the high-voltage DC bus of the latest ES660 host and relay card is above 800+V, the standard voltage bus is 100V DC, and the withstand voltage level of ESD and leakage circuit is 1200+V DC. This design enables the system to have high-voltage DC and latch testing capabilities (such as supporting LU bias and stress up to ± 300V). Highly modular design ensures sustainable upgrading of devices to support future higher pin counts and more advanced testing requirements. ES660The testing capability ensures efficient evaluation of large-scale devices, significantly reducing testing time and improving production efficiency.

Product Features

●The system configuration is highly flexible, supporting expansion from 128 pins to 2560 pins, and the number of buses can be configured from 1 to 12

●Capable of high specification testing, including 10kV HBM, 4kV MM, 300V/1A DC and latch stress, 1100V SMU leakage current testing

HBM tester based on low parasitic relay(Complies with JS-001 2017 Appendix B4, 2023/2024 Appendix C5 N=9 standards)

●ESD testing speed is fast (optional 10/15 pins per second, currently developing 20+pins per second)

● Compatible with multiple ESD/latch/transient latch testing methods and standards

● The voltage and current waveforms of the latch source can be captured and displayed through software (supporting multiple configurations with/without an oscilloscope)

Combined with external voltage and current probes, the ESD IV characteristic curve can be captured through software

● Optional temperature control forced module (optional range from room temperature to 200 ° C or -15 to 200 ° C)

Optional multi protocol preprocessing module to achieve interactive behavior in latch testing

Real time display of test progress and status on a 14 inch touch screen

● Support transient latch test configuration (can be combined with TLP/EOS/surge and other testing methods)

Product Application

Semiconductor ESD/EOS/LU testing

The HBM test configuration complies with ANSI/ESDA/JEDEC JS-001、MIL-STD-883E、AECQ100-002、AEC-Q-101-001、AEC-Q100-002 And GJB548C standard

The MM test configuration complies with ANSI/ESDA SP5.2JEDEC/JESD22-A115 standard

● Latch (LU) test:Compliant with JEDEC JESD78 and AEC-Q100-004 standards, supporting Overvoltage Test and I-Test

The transient latch (TLU) measurement configuration complies withANSI/ESD SP5.4.1 standard

ES660 ESD Electrostatic Discharge and Latch Testing SystemTechnical Specifications

Shanghai Zhengheng Electronic Technology Co., Ltd. shzhtechWe are a diversified company that integrates the agency sales of instruments and meters, the provision of testing solutions, pre-sales and after-sales technical support, and the maintenance of instruments and meters. Committed to providing professional and complete testing solutions, technical training, and maintenance services for customers in related fields.